As signal processing systems move to higher levels of integration, it becomes necessary to integrate analog functions on chips in which most of the area is consumed by digital circuitry. When the analog circuitry occupies only a small percentage of the total chip area, economic considerations limit the addition of any process steps, such as fabrication of high-value capacitors, which are not required by the digital circuits.
The switched capacitor (“SC”) filter provided a practical alternative. The original idea was to replace a resistor by a switched capacitor simulating the resistor. Thus the equivalent resistor could be implemented with a capacitor, and two switches operating with two clock phases. The basic building blocks involved in SC circuits are capacitors, MOSFET switches, and op-amps, which can be used to make higher-order blocks such as voltage gain amplifiers, integrators, and second-order filters. These are discrete-time filters that operate like continuous-time filters, but through the use of switches, the capacitance values can be kept very small. As a result, SC filters are amenable to VLSI implementations.
Infinite impulse response (IIR) is a property of signal processing systems. Systems with that property are known as IIR systems or when dealing with electronic filter systems as IIR filters. They have an impulse response function which is non-zero over an infinite length of time. This is in contrast to finite impulse response filters (FIR) which have fixed-duration impulse responses. The simplest analog IIR filter is an RC filter made up of a single resistor (R) feeding into a node shared with a single capacitor (C). This filter has an exponential impulse response characterized by an RC time constant.
The switching functions of the MOSFETs produces a discrete response rather than a continuous response from the filter. Therefore, Z Transforms are employed rather than S Transforms, and, just as in digital filters, aliasing effects occur. Any Z Transform approximation to a continuous function may be used to design a switched capacitor filter.
U.S. Pat. No. 7,079,826, “Digitally controlled analog RF filtering in subsampling communication receiver architecture” describes a method of down-converting a first periodic voltage waveform into a second periodic voltage waveform by sampling the first periodic waveform and transforming the first voltage waveform into a corresponding current waveform, integrating each half-cycle of the current waveform by charging a corresponding capacitor; and combining the samples to produce the second voltage waveform, and is incorporated herein by reference in its entirety.
U.S. Pat. No. 7,006,813, “Efficient charge transfer using a switched capacitor resistor” describes a method for setting a voltage on a sampling capacitor by applying a first substantially constant charging current to a charging capacitor for a first period of time to store a first charge on the charging capacitor, using the charging capacitor to share the first charge with the sampling capacitor, and leaving a residual charge on the charging capacitor; maintaining the residual charge on the charging capacitor after sharing with the sampling capacitor, and applying a second charging current to the charging capacitor for a second period of time to bring the charge on the charging capacitor from the residual charge to a second charge, and is incorporated herein by reference in its entirety.
U.S. Pat. No. 7,057,540, “Sigma-delta (.SIGMA..DELTA.) analog-to-digital converter (ADC) structure incorporating a direct sampling mixer” describes a sampling circuit using switched capacitors with low noise characteristics and at the same time is capable of providing a highly oversampled discrete-time sample stream, and is incorporated herein by reference in its entirety.
US Publication 20070105522, “Offset balancer, method of balancing an offset and a wireless receiver employing the balancer and the method” describes an offset balancer for use with a differential mixer employing wireless reception and an offset quantifier configured to indicate an existing DC offset of the mixer corresponding to an existing second-order intercept point applicable to the wireless reception, and is incorporated herein by reference in its entirety.